1. Field of the Invention
The present invention relates to a manufacturing method of semiconductor devices, in particular to an element isolation method on a substrate in terms of STI (Shallow Trench Isolation) method.
2. Description of the Related Art
In a semiconductor device, on a semiconductor substrate, constituent elements such as a transistor or diode, a capacitor, a resistance or the like are disposed to be electrically isolated from each other, these elements being interconnected with each other through wirings.
Recently, with higher integration and higher speed of the semiconductor devices, there is a strong demand for an improvement in the technique isolating these elements from each other.
In isolating the elements, in view of realizing excellent element characteristics, reliability and circuit performance, it is strongly desired to, while flattening a surface as much as possible, simplifying manufacturing steps and decreasing defect density, make an element isolation distance as small as possible.
The element isolation technique is roughly divided into LOCOS (Local Oxidation of Silicon) method and STI (Shallow Trench Isolation) method.
The LOCOS method where semiconductor substrate surface is selectively oxidized accompanies problems of erosion of an element formation region due to an occurrence of so-called bird's beak and of an occurrence of crystal defects due to an occurrence of local stress during formation of field oxide.
On the contrary, the STI method is advantageous in miniaturization. In specific, after forming a trench in an element isolation region by the RIE (reactive ion etching) method or the like, an oxide film as a filled material is deposited by the CVD (chemical vapor deposition) method for instance. The oxide layer deposited on a portion other than the trench is removed and flattened by use of CMP (chemical mechanical polishing method) to perform the element isolation.
A convnetional STI method will be explained with reference to FIGS. 8 to 11. On a silicon substrate 1, a silicon oxide film 2 and a silicon nitride film 3 are sequentially formed, thereafter by use of lithography technique and dry etching technique, with the silicon nitride film 3 as a protective layer, a silicon isolation trench 8 is formed. Thereafter, by of the CVD method, a second silicon oxide layer 4 is diposited in the silicon isolation trench 8 to fill the trench. The state up to this step is shown in FIG. 8.
Next, as shown in FIG. 9, the silicon oxide layer 4 is flattened by use of the CMP method, thereafter the silicon nitride film 3 that is a protective layer and the first silicon oxide film 2 being removed. Then, the filled silicon oxide layer 4 is thermally treated to form a STI isolation region.
In the conventional STI like the above, in removing the silicon oxide film 2, an etching liquid such as BHF is usually used. However, the etching liquid permeates into an interface between the silicon substrate 1 and the filled silicon oxide layer 4 to result in a rapid etching at the interface. As a result, as shown in FIG. 10, a divot 7 occurs.
A final thermal treatment is performed to densify. However, because of an oxidizing atmosphere, silicon tends to be oxidized, as a result, as shown in FIG. 10, the STI region undergoes changes. That is, the width of the isolation trench 8 (conversion difference) becomes larger to result in a difficulty in miniaturizing.
Further, after forming the isolation region, an impurity (P or B) is introduced in the element formation region to form a transistor. However, as shown in FIG. 11, through the second filled oxide layer 4 from the trench portion, the impurity diffuses to the external to result in a decrease of the impurity concentration.
In order to overcome the aforementioned disadvantages, Japanese Patent Laid-open Application No. HEI 11-3936 discloses an element isolation method for semiconductor devices. In which, on a wall surface of an isolation trench a silicon oxide film is formed by thermal oxidation, or further on the silicon oxide film formed on the wall surface of the trench a silicon nitride film is deposited. Then, a silicon oxide film is deposited on the substrate by the CVD method, further heat treating the entire substrate in a high-pressure atmosphere.
Further, Japanese Patent Laid-open Application No. HEI 11-45996 discloses a method for manufacturing semiconductor devices. In which, a silicon substrate is directly nitrided, or with a silicon nitride film as a mask nitrogen ions are selectively injected into an isolation trench sidewall or a bottom surface thereof, to diffuse nitrogen atoms into the silicon substrate. Due to the action of the nitrogen atoms, channel impurities are suppressed from diffusing into the trench filled oxide layer.
However, when a nitride film is deposited between the filled oxide layer and the silicon substrate, the nitride film, having a tendency of easily trapping charges, is liable to affect electrically adversely on a transistor.
As mentioned above, in the conventional STI, there have been problems that the divot occurs at an upper interface between the silicon substrate and the filled oxide layer and due to the large isolation width the miniaturization becomes difficult. Further, there is a likelihood that the impurity doped after formation of the isolation region goes therethrough to lower the impurity concentration to result in deteriorating element characteristics. When inserting a nitride film between the silicon substrate and the filled oxide layer to overcome these problems, there occurs a new problem that due to the charge trap an electrically adverse influence is caused.